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Exercises in Software Generator Code 3 of 9 in Software Exercises




How to generate, print barcode using .NET, Java sdk library control with example project source code free download:
Exercises use software barcode 39 printer todevelop barcode code39 in software 2/5 Industrial Z is asserted should be sp Software barcode code39 aced as evenly as possible, that is, every second tick when N = 8, every fourth when N = 4, and so on.) Modify the circuit of Exercise 8.29 so that Z produces N transitions in each 16tick interval.

The resulting circuit is called a binary rate multiplier, and was once sold as a TTL MSI part, the 7497. (Hint: Gate the clock with the level output of the previous circuit.) A digital designer (the author!) was asked at the last minute to add new functionality to a PCB that had room for just one more 16-pin IC.

The PCB already had a 16-MHz clock signal, MCLK, and a spare microprocessor-controlled select signal, SEL. The designer was asked to provide a new clock signal, UCLK , whose frequency would be 8 MHz or 4 MHz depending on the value of SEL. To make things worse, the PCB had no spare SSI gates, and UCLK was required to have a 50% duty cycle at both frequencies.

It took the designer about five minutes to come up with a circuit. Now it s your turn to do the same. (Hint: The designer had long considered the 74x163 to be the fundamental building block of tricky sequential-circuit design.

) Design a modulo-16 counter, using one 74x169 and at most one SSI package, with the following counting sequence: 7, 6, 5, 4, 3, 2, 1, 0, 8, 9, 10, 11, 12, 13, 14, 15, 7, . Modify the VHDL program in Table 8-14 so that the type of ports D and Q is STD_LOGIC_VECTOR, including conversion functions as required. Modify the program in Table 8-16 to use structural VHDL, so it conforms exactly to the circuit in Figure 8-45, including the signal names shown in the figure.

Define and use any of the following entities that don t already exist in your VHDL library: AND2, INV, NOR2, OR2, XNOR2, Vdffqqn. Modify the program in Table 8-17 to use VHDL s generic statement, so that the counter size can be changed using the generic definition. Design a parallel-to-serial conversion circuit with eight 2.

048 Mbps, 32-channel serial links and a single 2.048 MHz, 8-bit, parallel data bus that carries 256 bytes per frame. Each serial link should have the frame format defined in Figure 8-55.

Each serial data line SDATAi should have its own sync signal SYNCi; the sync pulses should be staggered so that SYNCi + 1 has a pulse one clock tick after SYNCi. Show the timing of the parallel bus and the serial links, and write a table or formula that shows which parallel-bus timeslots are transmitted on which serial links and timeslots. Draw a logic diagram for the circuit using MSI parts from this chapter; you may abbreviate repeated elements (e.

g., shift registers), showing only the unique connections to each one. Repeat Exercise 8.

36, assuming that all serial data lines must reference their data to a single, common SYNC signal. How many more chips does this design require Show how to enhance the serial-to-parallel circuit of Exercise 8-57 so that the byte received in each timeslot is stored in its own register for 125 s, until the next byte from that timeslot is received. Draw the counter and decoding logic for 32 timeslots in detail, as well as the parallel data registers and connections for.

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53 Copyright 1999 by John F. Wakerly. timeslots 31, 0, and 1. Al so draw a timing diagram in the style of Figure 8-58 that shows the decoding and data signals associated with timeslots 31, 0, and 1. Suppose you are asked to design a serial computer, one that moves and processes data one bit at a time.

One of the first decisions you must make is which bit to transmit and process first, the LSB or the MSB. Which would you choose, and why Design an 8-bit self-correcting ring counter whose states are 11111110, 11111101, , 01111111, using only two SSI/MSI packages. Design two different 2-bit, 4-state counters, where each design uses just a single 74x74 package (two edge-triggered D flip-flops) and no other gates.

Design a 4-bit Johnson counter and decoding for all eight states using just three SSI/MSI packages. Your counter need not be self-correcting. Starting with state 0001, write the sequence of states for a 4-bit LFSR counter designed according to Figure 8-68 and Table 8-21.

Prove that an even number of shift-register outputs must be connected to the oddparity circuit in an n-bit LFSR counter if it generates a maximum-length sequence. (Note that this is a necessary but not a sufficient requirement. Also, although Table 8-21 is consistent with what you re supposed to prove, simply quoting the table is not a proof!) Prove that X0 must appear on the right-hand side of any LFSR feedback equation that generates a maximum-length sequence.

(Note: Assume the LFSR bit ordering and shift direction are as given in the text; that is, the LFSR counter shifts right, toward the X0 stage.) Suppose that an n-bit LFSR counter is designed according to Figure 8-68 and Table 8-21. Prove that if the odd-parity circuit is changed to an even-parity circuit, the resulting circuit is a counter that visits 2 n 1 states, including all of the states except 11 11.

Find a feedback equation for a 3-bit LFSR counter, other than the one given in Table 8-21, that produces a maximum-length sequence. Given an n-bit LFSR counter that generates a maximum-length sequence (2 n 1 states), prove that an extra XOR gate and an n 1 input NOR gate connected as suggested in Figure 8-69 produces a counter with 2 n states. Prove that a sequence of 2 n states is still obtained if a NAND gate is substituted for a NOR above, but that the state sequence is different.

Design an iterative circuit for checking the parity of a 16-bit data word with a single even parity bit. Does the order of bit transmission matter Modify the shift-register program in Table 8-23 to provide an asynchronous clear input using a 22V10. Write an ABEL program that provides the same functionality as a 74x299 shift register.

Show how to fit this function into a single 22V10 or explain why it does not fit. In what situations do the ABEL programs in Tables 8-26 and 8-27 give different operational results .
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